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Design of high-end field programmable gate array (FPGA) using Mentor Graphics design tools such as ModelSim and Precision RTL.

 

Program Duration: 30 hours
Program Language: English / Arabic
Location: EPSILON TRAINING CENTER | Head Office

 

Participants will be granted a completion certificate from Epsilon Training Institute, USA if they attend a minimum of 80 percent of the direct contact hours of the Program and after fulfilling program requirements (passing both Final Exam and Project to obtain the Certificate)

 

Course Outline

  • Hierarchical design
  • Hardware description languages such as VHDL
  • Synthesis
  • Design verification
  • IC test
  • Chip-scale synchronous design
  • Case studies

For the project, Trainees will design and implement a significant digital signal processing system using high-end

Course Curriculum

Hierarchical design
Hardware description languages such as VHDL
Synthesis
Design verification
IC test
Chip-scale synchronous design
Case studies

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